Semiconductor device having wafer-level chip size package

ABSTRACT

A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of application Ser. No.12/960,717 filed Dec. 6, 2010, which is a divisional of application Ser.No. 12/489,544 filed Jun. 23, 2009, now U.S. Pat. No. 7,884,008, whichis a divisional application of application Ser. No. 11/294,502 filed onDec. 6, 2005, now U.S. Pat. No. 7,582,972, which are hereby incorporatedfor all purposes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a small semiconductor device such as adevice with a wafer level chip size package, and to the fabrication ofthis type of semiconductor device, more particularly to the fabricationof electrodes on the surface of the package and their interconnectionsto pads on the semiconductor device within the package.

2. Description of the Related Art

With the recent rising demand for smaller, slimmer semiconductorintegrated circuits, wafer level chip size packages have becomeprevalent, especially for thin semiconductor devices. A wafer level chipsize package (WCSP) is simply a protective layer with a grid ofhemispherical bump electrodes, formed on a semiconductor integratedcircuit in the wafer processing stage before the wafer is diced intoindividual integrated circuit chips. WCSP semiconductor devices as thinas three-tenths of a millimeter (0.3 mm) have been developed.

In a conventional semiconductor device of the WCSP type, integratedcircuits formed on the front major surface of the wafer are covered by adielectric layer on which there are electrode pads electricallyconnected to the circuitry below. An interlayer dielectric film is thendeposited, holes extending to the electrode pads are formed in thisfilm, a layer of metal is deposited, filling the holes, and a conductivepattern of redistribution wiring is formed, extending from the holes tothe grid sites where bump electrodes will be placed. Posts about onehundred micrometers (100 μm) high are created at these sites by coatingthe wafer with a layer of photoresist, forming holes in the photoresistlayer, filling the holes with metal, and then removing the photoresist.The surface of the wafer is then sealed in a layer of resin injected inliquid form, after which the surface is polished to expose the posts,and hemispherical bumps are formed on the exposed ends of the posts.After this the wafer is diced into separate semiconductor devices. (See,for example, Japanese Patent Application Publication No. 2003-60120).

A problem with this process is that even after polishing, the resinlayer is nearly as thick (e.g., 90 μm thick) as the original height ofthe posts, and takes up much of the total thickness (e.g., 30%) of thesemiconductor device.

It is also known art to form bump electrodes without forming posts.(See, for example, Japanese Patent Application Publication No.H11-195665 and U.S. Pat. No. 6,621,164.)

SUMMARY OF THE INVENTION

An object of the present invention is to reduce the thickness of asemiconductor device having a wafer-level chip size package.

The invented semiconductor device includes a semiconductor substratehaving a first surface, a second surface opposed to the first surface,and a circuit element formed on the first surface. An electrode paddisposed on the first surface is electrically coupled to the circuitelement. A first metal layer is formed on the electrode pad, and aconductive pattern is formed on the first metal layer. The first-surfaceside of the semiconductor substrate is sealed by a protective layerhaving an opening exposing part of the conductive pattern. The openingis covered by an electrode that is electrically coupled to the part ofthe conductive pattern disposed within the opening.

This structure enables the thickness of the protective layer (thepackage layer in a wafer level chip size package) to be reduced becausethe electrode is connected directly to the conductive pattern. Theprotective layer may comprise a photosensitive material, whichsimplifies the formation of the opening for the electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

In the attached drawings:

FIGS. 1, 2, 3, 4, 5, 6, and 7 illustrate steps in a semiconductor devicefabrication process according to a first embodiment of the invention;

FIGS. 8, 9, 10, 11, 12, 13, 14, and 15 illustrate steps in asemiconductor device fabrication process according to a secondembodiment;

FIGS. 16, 17, 18, 19, 20, 21, 22, 23, 24, and 25 illustrate steps in asemiconductor device fabrication process according to a thirdembodiment;

FIGS. 26, 27, 28, 29, 30, 31, and 32 illustrate steps in a semiconductordevice fabrication process according to a fourth embodiment;

FIGS. 33, 34, 35, 36, 37, 38, 39, and 40 illustrate steps in asemiconductor device fabrication process according to a fifthembodiment;

FIGS. 41, 42, 43, 44, 45, 46, 47, and 48 illustrate steps in asemiconductor device fabrication process according to a sixthembodiment;

FIGS. 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, and 59 illustrate steps ina semiconductor device fabrication process according to a seventhembodiment;

FIGS. 60, 61, 62, 63, 64, 65, 66, 67, 68, and 69 illustrate steps in asemiconductor device fabrication process according to an eighthembodiment; and

FIGS. 70, 71, 72, 73, 74, 75, 76, and 77 illustrate steps in asemiconductor device fabrication process according to a ninthembodiment.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention will now be described with reference to theattached drawings, in which like elements are indicated by likereference characters. The drawings illustrate steps in the fabricationof semiconductor devices embodying the present invention. Each drawingis a cross-sectional view of the region of a semiconductor wafer aroundone electrode pad; the drawings illustrate the formation of a bumpelectrode and wiring connecting the bump electrode to the electrode pad.After the illustrated steps, the wafer will be diced into integratedcircuit chips, each having a plurality of electrode pads and bumpelectrodes of the type illustrated.

First Embodiment

The first embodiment is a semiconductor device fabricated from a wafer 1as illustrated in FIGS. 1 to 7.

The semiconductor wafer 1 includes a semiconductor substrate 2 having afront surface (the first surface, the upper surface in the drawings) anda back surface (the second surface, the lower surface in the drawings).The front surface is also referred to as the circuit surface 3, becauseit includes a plurality of interconnected circuit elements such astransistors (not shown). The circuit surface 3 is covered by adielectric layer 4 of silicon dioxide with openings referred to ascontact holes (not shown) leading to circuit elements on the circuitsurface 3. The surface of the dielectric layer 4 is covered with aconductive metal film such as an aluminum film (not shown). The metal ispatterned to form interconnection wiring (not shown) that iselectrically coupled to the circuitry on the circuit surface 3 throughthe contact holes.

Patterning of the conductive metal film also produces a plurality ofelectrode pads 5, one of which is shown in the drawings. Each electrodepad 5 is electrically coupled to a corresponding circuit element on thecircuit surface 3. The dielectric layer 4 is covered by a surfaceprotection layer 6 of silicon nitride, which also covers the edges ofthe electrode pads 5. An interlayer dielectric film 7 of polyimide resinis formed on the surface protection layer 6, with through holes 8extending to the electrode pads 5, to reduce stress applied to thesemiconductor substrate 2.

A metal underlayer 9 is deposited as a multilayer film on the entirefront surface of the semiconductor wafer 1 by sputtering, covering theinterlayer dielectric film 7, the inner walls of the through holes 8,and the electrode pads 5. A conductive pattern of redistribution wiring,referred to below as a redistribution pattern 10, is formed byselectively electro-depositing copper on the surface of the metalunderlayer 9, using a photoresist mask 17 (FIG. 3) that exposes only theparts of the metal underlayer 9 disposed above the electrode pads 5, theparts of the metal underlayer 9 disposed in electrode areas 11 in whichbump electrodes 15 (FIG. 7) will be formed, and an interconnecting partthat connects each electrode pad 5 to one electrode area 11. The metalunderlayer 9 is removed after the electro-deposition process, except forthe parts disposed beneath the redistribution pattern 10.

The front surface of the semiconductor substrate 2 is sealed by aprotective layer 12 formed by curing a positive or negativephotosensitive resin, such as an epoxy resin or polyimide resin, byselective exposure to ultraviolet light, which makes the resin soluble(if positive) or insoluble (if negative) in a chemical developingsolution. In the first embodiment, the protective layer 12 is formed bycuring a negative photosensitive resin using polybenzoxazole that, whenexposed to ultraviolet light, becomes hardened and insoluble in thedeveloping solution.

After development, the uncured parts of the protective layer 12 becomeelectrode openings 13 that extend to and expose the redistributionpattern 10 in the electrode areas 11. The bump electrodes 15 are formedby melting solder balls printed on the electrode areas 11, so that thebump electrodes 15 cover the electrode areas 11 and make directelectrical contact with the redistribution pattern 10 at the bottom ofeach electrode opening 13.

A fabrication method for the semiconductor device in the firstembodiment includes the steps P1 to P7 illustrated in FIGS. 1 to 7.

In step P1 in FIG. 1, a plurality of interconnected circuit elements(not shown) are formed on the circuit surface 3 of the semiconductorsubstrate 2, which is a generally circular wafer formed by slicing acylindrical bar of silicon. The circuit surface 3 is covered by thedielectric layer 4 having contact holes (not shown) leading to thecircuit elements on the circuit surface 3, an aluminum film is sputteredonto the surface of the dielectric layer 4, and the aluminum metal ispatterned by photolithography and etching to produce a plurality ofelectrode pads 5. Each electrode pad 5 is electrically coupled to acorresponding circuit element on the circuit surface 3 through acorresponding contact hole.

After formation of the electrode pads 5, the surface protection layer 6of silicon nitride is deposited on the surfaces of the electrode pads 5and the dielectric layer 4 by chemical vapor deposition (CVD), part ofthe surface protection layer 6 on the surfaces of the electrode pads 5is removed by etching, the interlayer dielectric film 7 of polyimideresin is formed on the surface protection layer 6 and the electrode pads5, and part of the interlayer dielectric film 7 on the surfaces of theelectrode pads 5 is removed by etching to form through holes 8 extendingto the electrode pads 5.

In step P2 in FIG. 2, the multilayer metal underlayer 9 is sputteredonto the entire front surface of the semiconductor wafer 1, covering theinterlayer dielectric film 7 and the electrode pads 5.

In step P3 in FIG. 3, the photoresist mask 17 is formed. The photoresistmask 17 covers all parts of the metal underlayer 9 except for the parts,extending from the surfaces of the electrode pads 5 to the electrodeareas 11, in which the redistribution pattern 10 will be formed. Thephotoresist mask 17 comprises a positive or negative photoresistmaterial that is spin-coated onto the wafer 1 and then patterned byphotolithography. Photolithography in this case means exposing thephotoresist material to light through a mask and then chemicallydeveloping the photoresist material. Copper is electro-deposited on theuncovered surface of the metal underlayer 9, using the metal underlayer9 as a negative electrode, to form the redistribution pattern 10.

In step P4 in FIG. 4, the photoresist mask 17 that was formed in step P3is removed with a solvent such as acetone.

In step P5 in FIG. 5, the metal underlayer 9, except for the part belowthe redistribution pattern 10, is removed by plasma etching in an oxygenatmosphere.

In step P6 in FIG. 6, a polybenzoxazole photosensitive resin is appliedto the entire front surface of the semiconductor wafer 1 by aspin-coating process, and the applied photosensitive resin is exposed toultraviolet light with a photoresist mask masking the electrode areas11, curing the photosensitive resin except the part in the maskedelectrode areas 11. The unexposed photosensitive resin is removed bychemical development, leaving a protective layer 12 about fivemicrometers (5 μm) thick with electrode openings 13 measuring about twohundred micrometers (200 μm) in diameter extending to the redistributionpattern 10 in the electrode areas 11.

In step P7 in FIG. 7, flux is applied to the redistribution pattern 10that is exposed at the bottom of each electrode opening 13 in theprotective layer 12. A template (not shown) having approximately thesame diameter as the semiconductor wafer 1 and having apertures slightlylarger in diameter than the solder balls is mounted on the wafer. Thesolder balls are dropped into the apertures and thereby emplaced in theelectrode openings 13 of the protective layer 12; then the template isremoved and a heat treatment or reflow process is performed to melt thesolder balls, thereby forming hemispherical bump electrodes 15 thatproject from the front surface of the protective layer 12 and aredirectly joined to the redistribution pattern 10 exposed at the bottomof the electrode openings 13.

After steps P1 to P7 above, the semiconductor wafer 1 is diced intoindividual integrated circuit chips, each including a plurality ofsemiconductor circuit elements. Each chip is a separate WCSPsemiconductor device.

Since a WCSP semiconductor device fabricated as described above includesa plurality of bump electrodes 15 projecting from the front surface ofthe protective layer 12 of the semiconductor device and directly joinedto the redistribution pattern 10, instead of being formed on posts, nothick resin layer is required to seal the posts. The method described inthe first embodiment can be used to fabricate WCSP semiconductor deviceswith thicknesses as small as twenty-two hundredths of a millimeter (0.22mm).

The use of a photosensitive material for the protective layer 12 thatseals the front surface of the semiconductor device simplifies theformation of the electrode openings 13 for the bump electrodes 15.

Application of flux to the electrode openings 13 before the solder ballsare placed in the electrode openings 13 and melted secures reliablesolder joints between the redistribution pattern 10 and the bumpelectrodes 15 by blocking air currents.

Compared with conventional WCSP fabrication processes that form posts,the fabrication process described in the first embodiment has fewersteps: specifically, it does not require steps to form a photoresistlayer defining the posts, to form the posts, and then to remove thephotoresist layer; it is also unnecessary to polish the front surface ofthe resin protective layer to expose the ends of the posts beforeforming the bump electrodes. WCSP semiconductor devices according to thefirst embodiment can accordingly be fabricated more efficiently and in ashorter time than devices having posts.

As described above, in the first embodiment, the front surface of asemiconductor device is sealed by a protective layer having openingsexposing part of a redistribution pattern of conductive traces. Theopenings are covered by bump electrodes that make direct contact withthe redistribution pattern. This structure enables the thickness of theprotective layer (the package layer in a wafer level chip size package)to be reduced. The protective layer may comprise a photosensitivematerial, which simplifies the formation of the openings for theelectrodes.

Second Embodiment

The second embodiment is a semiconductor device fabricated from a wafer1 as illustrated in FIGS. 8 to 15.

The second embodiment differs from the first embodiment by includingconductive nubs referred to below as redistribution nubs 21, seen inFIGS. 12 to 15. The redistribution nubs 21 are cylindrical projectionsof the same material as the redistribution pattern 10, and are formed inthe electrode areas 11, making direct electrical contact with theredistribution pattern 10.

A fabrication method for the semiconductor device in the secondembodiment includes the steps PA1 to PA8 illustrated in FIGS. 8 to 15.

Since steps PA1 to PA4 in FIGS. 8 to 11 are the same as steps P1 to P4in FIGS. 1 to 4 in the first embodiment, descriptions will be omitted.

In step PA5 in FIG. 12, a second photoresist mask 17 is formed (thisphotoresist mask is different from the photoresist mask used in step PA3in FIG. 10). The second photoresist mask 17 covers all parts of themetal underlayer 9 and the redistribution pattern 10 except for theparts of the metal underlayer 9 below the redistribution pattern 10 andthe parts of the redistribution pattern 10 in the electrode areas 11.The photoresist mask 17 is a positive or negative photoresist materialthat is patterned by photolithography. Copper is electro-deposited onthe exposed parts of the redistribution pattern 10, using the metalunderlayer 9 as a negative electrode, to form the redistribution nubs21.

In step PA6 in FIG. 13, the photoresist mask 17 that was formed in stepPA5 is removed with a solvent, and the metal underlayer 9, except forthe part below the redistribution pattern 10, is removed as in step P5in the first embodiment.

In step PA7 in FIG. 14, a photosensitive resin is applied to the entirefront surface of the semiconductor wafer 1 by a spin-coating process,and the applied photosensitive resin is exposed to ultraviolet light,curing the photosensitive resin, except for the parts residing on theredistribution nubs 21, which are masked. The unexposed photosensitiveresin on the redistribution nubs 21 is removed by chemical development,leaving a protective layer 12 about 5 μm thick with redistribution nubs21 projecting from the protective layer 12.

In step PA8 in FIG. 15, flux is applied to the redistribution nubs 21that project from the front surface of the semiconductor wafer 1. Solderballs are emplaced on the ends of the redistribution nubs 21 with atemplate as in step P7 in the first embodiment; then a heat treatmentprocess is performed to melt the solder balls, thereby forminghemispherical bump electrodes 15 that cover the redistribution nubs 21projecting from the protective layer 12.

After steps PA1 to PA8 above, the semiconductor wafer 1 is diced intoindividual integrated circuit chips, each including a plurality ofsemiconductor circuit elements. Each chip is a separate WCSPsemiconductor device.

Since a WCSP semiconductor device fabricated as described above includesa plurality of bump electrodes 15 projecting from the front surface ofthe protective layer 12 of the semiconductor device and electricallycoupled to the redistribution pattern 10 through the redistribution nubs21, instead of being formed on posts, a thin resin layer suffices toseal the front surface of the semiconductor device. The method describedin the second embodiment can therefore be used to fabricate WCSPsemiconductor devices with reduced thicknesses.

The use of a photosensitive material for the protective layer 12 thatseals the front surface of the semiconductor device simplifies theformation of the protective layer 12 around the projectingredistribution nubs 21. Compared with conventional WCSP fabricationprocesses that form posts, the fabrication process described in thesecond embodiment has fewer steps because it is unnecessary to polishthe front surface of the resin protective layer to expose the ends ofthe posts before forming the bump electrodes. WCSP semiconductor devicesaccording to the second embodiment can accordingly be fabricated moreefficiently and in a shorter time than devices having posts.

The large area of both vertical and horizontal contact between thehemispherical bump electrodes 15 and the projecting redistribution nubs21 assures reliable solder joints between the bump electrodes 15 and theredistribution nubs 21. After the semiconductor device is mounted on aprinted circuit board or card, the redistribution nubs 21 absorbexternal stress applied to the bump electrodes 15, making the externalelectrical connections of the semiconductor device still more reliable.

As described above, in the second embodiment, the front surface of asemiconductor device is sealed by a protective layer with openings forprojecting conductive nubs, which are formed on the redistributionpattern, and bump electrodes are formed on the nubs. The protectivelayer may comprise a photosensitive material, which simplifies removalof the protective material from the nubs. The projecting structureenables the thickness of the protective layer (the package layer in awafer level chip size package) to be reduced, and allows secure jointsto be formed between the bump electrodes and the nubs, so thesemiconductor device is electrically coupled to external devices withhigh reliability.

Third Embodiment

The third embodiment is a semiconductor device fabricated from a wafer 1as illustrated in FIGS. 16 to 25.

The third embodiment differs from the first embodiment by including asecond metal underlayer 23 and conductive redistribution nubs 24. InFIG. 22, the second metal underlayer 23 is deposited as a multilayerfilm on the entire front surface of the protective layer 12 bysputtering, as was the metal underlayer 9 in the first embodiment, andis patterned by etching to cover the edges of the electrode openings 13in the protective layer 12, the exposed parts of redistribution pattern10 at the bottom of the electrode openings 13, and the inner walls ofthe electrode openings 13.

The conductive redistribution nubs 24 are generally cylindricalprojections of the same material as the redistribution pattern 10. Theconductive redistribution nubs 24 have large-diameter and small-diameterparts, and are formed on the electrode areas 11, making directelectrical contact with the second metal underlayer 23.

A fabrication method for the semiconductor device in the thirdembodiment includes the steps PB1 to PB10 illustrated in FIGS. 16 to 25.

Since steps PB1 to PB6 in FIGS. 16 to 21 are the same as steps P1 to P6in FIGS. 1 to 6 in the first embodiment, descriptions will be omitted.In step PB2, the first metal underlayer 9 is deposited on the entirefront surface of the semiconductor substrate 2.

In step PB7 in FIG. 22, the multilayer second metal underlayer 23 issputtered onto the entire front surface of the wafer, covering theprotective layer 12, the exposed parts of the redistribution pattern 10at the bottom of the electrode openings 13, and the inner walls of theelectrode openings 13.

In step PB8 in FIG. 23, the photoresist mask 17 is formed. Thephotoresist mask 17 covers all parts of the second metal underlayer 23except for the electrode openings 13 and the edges of the electrodeopenings 13. The photoresist mask 17 is a positive or negativephotoresist material that is patterned by photolithography. Copper iselectro-deposited on the exposed parts of the second metal underlayer23, using the second metal underlayer 23 as a negative electrode, toform the conductive redistribution nubs 24. The large-diameter parts ofthe conductive redistribution nubs 24 project from the protective layer12.

In step PB9 in FIG. 24, the photoresist mask 17 that was formed in stepPB8 is removed with a solvent, and the second metal underlayer 23,except for the parts below the conductive redistribution nubs 24, isremoved as in step P5 in the first embodiment.

In step PB10 in FIG. 25, flux is applied to the parts of the conductiveredistribution nubs 24 that project from the front surface of thesemiconductor wafer 1. Solder balls are emplaced at the ends of theconductive redistribution nubs 24 with a template as in step P7 in thefirst embodiment; then a heat treatment process is performed to melt thesolder balls, thereby forming hemispherical bump electrodes 15 thatcover the large-diameter parts of the conductive redistribution nubs 24projecting from the protective layer 12.

After steps PB1 to PB10 above, the semiconductor wafer 1 is diced intoindividual integrated circuit chips, each including a plurality ofsemiconductor circuit elements. Each chip is a separate WCSPsemiconductor device.

Since a WCSP semiconductor device fabricated as described above includesa plurality of bump electrodes 15 projecting from the front surface ofthe protective layer 12 of the semiconductor device and electricallycoupled to the redistribution pattern 10 through the conductiveredistribution nubs 24 and the second metal underlayer 23, instead ofbeing formed on posts, a thin resin layer suffices to seal the frontsurface of the semiconductor device. The method described in the thirdembodiment can therefore be used to fabricate WCSP semiconductor deviceswith reduced thicknesses.

Use of a photosensitive protective layer 12 to seal the front surface ofthe semiconductor device simplifies the formation of the electrodeopenings 13 for the conductive redistribution nubs 24.

The conductive redistribution nubs 24 are joined to the exposed parts ofthe redistribution pattern 10 at the bottom of the electrode openings13, to the inner walls of the electrode openings 13, and to the edges ofthe protective layer 12 surrounding the electrode openings 13 throughthe second metal underlayer 23. The hemispherical bump electrodes 15cover the parts of the conductive redistribution nubs 24 that projectfrom the protective layer 12. The joints between the bump electrodes 15and the conductive redistribution nubs 24 are highly reliable, as in thesecond embodiment, and the joints between the conductive redistributionnubs 24 and the semiconductor wafer 1 are also highly reliable, so thereliability of the external electrical connections of the semiconductordevice is further improved.

As described above, in the third embodiment, the front surface of asemiconductor device is sealed by a protective layer having openingsexposing parts of a redistribution pattern. A metal underlayer coversthe exposed parts of the redistribution pattern as well as the innerwalls and upper edges of the openings. A metal nub, formed on this metalunderlayer, projects from each opening in the protective layer. A bumpelectrode is placed on the nub. The protective layer may comprise aphotosensitive material, which simplifies the formation of the openingsfor the nubs. This structure provides secure joints between the bumpelectrodes and the nubs, and secure joints between the nubs and thesemiconductor device, so the external electrical connections of thesemiconductor device are highly reliably.

Fourth Embodiment

The fourth embodiment is a semiconductor device fabricated from a wafer1 as illustrated in FIGS. 26 to 32.

The fourth embodiment differs from the first embodiment by includinginterlayer dielectric nubs 26, with corresponding differences in themetal underlayer 9, redistribution pattern 10, and bump electrodes 15.As shown in FIG. 26, the interlayer dielectric nubs 26 are cylindricalprojections of the interlayer dielectric film 7. The interlayerdielectric nubs 26 and the interlayer dielectric film 7 are formed bytwice curing a negative photosensitive resin, such as a polyimide resin.

A fabrication method for the semiconductor device in the fourthembodiment includes the steps PC1 to PC7 illustrated in FIGS. 26 to 32.

In step PC1 in FIG. 26, a plurality of interconnected circuit elementsare formed on the circuit surface 3 of the semiconductor substrate 2;the dielectric layer 4, the electrode pads 5, and the surface protectionlayer 6 are formed; and the surface protection layer 6 is partly removedfrom the surfaces of the electrode pads 5, as in step P1 in the firstembodiment.

A comparatively thick coat of negative photosensitive polyimide resin isapplied to the surfaces of the surface protection layer 6 and theelectrode pads 5 by a spin-coating process, and the appliedphotosensitive resin coating is exposed to ultraviolet light through amask that masks the through holes 8, curing the lower part of thephotosensitive resin coating elsewhere to the thickness of theinterlayer dielectric film 7. The photosensitive resin in the electrodeareas 11, which will become the interlayer dielectric nubs 26, isexposed to ultraviolet light again through a mask that masks all partsexcept for the electrode areas 11, curing the resin in the electrodeareas 11 to the additional thickness of the interlayer dielectric nubs26 so that when the redistribution pattern 10 is formed later (FIG. 28),the parts of the redistribution pattern 10 formed on the surfaces of theinterlayer dielectric nubs 26 will project from the front surface of theprotective layer 12. The unexposed photosensitive resin is then removedby chemical development, leaving the through holes 8 extending to theelectrode pads 5 and forming the interlayer dielectric film 7 and theinterlayer dielectric nubs 26.

In step PC2 in FIG. 27, the metal underlayer 9 is sputtered onto theentire front surface of the semiconductor wafer 1, covering theinterlayer dielectric nubs 26, the interlayer dielectric film 7, and theelectrode pads 5 as in step P2 in the first embodiment.

In step PC3 in FIG. 28, a photoresist mask 17 is formed. The photoresistmask 17 covers all parts of the metal underlayer 9 except for the parts,extending from the surfaces of the electrode pads 5 to the interlayerdielectric nubs 26 in the electrode areas 11, in which theredistribution pattern 10 will be formed. The photoresist mask 17comprises a positive or negative photoresist material that is patternedby photolithography. The redistribution pattern 10 is formed on theexposed surface of the metal underlayer 9 as in step P3 in the firstembodiment.

In step PC4 in FIG. 29, the photoresist mask 17 that was formed in stepPC3 is removed with a solvent.

In step PC5 in FIG. 30, the metal underlayer 9, except for the partbelow the redistribution pattern 10, is removed as in step P5 in thefirst embodiment.

In step PC6 in FIG. 31, a photosensitive resin is applied to the entirefront surface of the semiconductor wafer 1 by a spin-coating process,and the applied photosensitive resin is exposed to ultraviolet light,curing the photosensitive resin, except for the parts residing in theelectrode areas 11, which are masked. The unexposed photosensitive resinis removed by chemical development, leaving a protective layer 12 about5 μm thick with parts of the redistribution pattern 10 projecting fromthe protective layer 12 in the electrode areas 11.

In step PC7 in FIG. 32, flux is applied to the parts of theredistribution pattern 10 that project from the front surface of thesemiconductor wafer 1. Solder balls are emplaced at the ends of theparts of the redistribution pattern 10 in the electrode areas 11 with atemplate as in step P7 in the first embodiment; then a heat treatmentprocess is performed to melt the solder balls, thereby forminghemispherical bump electrodes 15 that cover the parts of theredistribution pattern 10 projecting from the protective layer 12.

After steps PC1 to PC7 above, the semiconductor wafer 1 is diced intoindividual integrated circuit chips, each including a plurality ofsemiconductor circuit elements. Each chip is a separate WCSPsemiconductor device.

Since a WCSP semiconductor device fabricated as described above includesa plurality of bump electrodes 15 that project from the front surface ofthe protective layer 12 of the semiconductor device and are formed onparts of the redistribution pattern 10 that also project from theprotective layer 12, instead of being formed on posts, a thin resinlayer suffices to seal the front surface of the semiconductor device.The method described in the fourth embodiment can therefore be used tofabricate WCSP semiconductor devices with reduced thicknesses.

Use of a photosensitive protective layer 12 to seal the front surface ofthe semiconductor device simplifies the formation of the protectivelayer 12 around the projecting parts of the redistribution pattern 10.

In step PC1, a comparatively heavy coat of negative photosensitive resinis applied to the surfaces of the surface protection layer 6 and theelectrode pads 5. The applied photosensitive resin is exposed toultraviolet light through a mask masking the through holes 8; then thephotosensitive resin is exposed to ultraviolet light again throughanother mask masking the parts of the interlayer dielectric film 7 inthe electrode areas 11, thereby forming the interlayer dielectric film 7and the interlayer dielectric nubs 26 in one step. This comparesfavorably with conventional WCSP fabrication processes that use threesteps to form posts (a step of forming a photoresist layer defining theposts, a step of forming the posts, and a further step of removing thephotoresist layer) and must then polish the front surface of the resinprotective layer to expose the ends of the posts before forming the bumpelectrodes. WCSP semiconductor devices according to the fourthembodiment can accordingly be fabricated more efficiently and in ashorter time than devices having posts.

The hemispherical bump electrodes 15 cover the parts of theredistribution pattern 10 that are formed on the interlayer dielectricnubs 26 and project from the protective layer 12, thereby securingreliable solder joints between the bump electrodes 15 and theredistribution pattern 10. After the semiconductor device is mounted ona printed circuit board or card, the redistribution pattern 10 andinterlayer dielectric nubs 26 absorb external stress applied to the bumpelectrodes 15, making the external electrical connections of thesemiconductor device more reliable.

As described above, in the fourth embodiment, the front surface of asemiconductor device is sealed by a protective layer. Parts of aredistribution pattern that are formed on nubs project from theprotective layer, and bump electrodes are placed on those parts of theredistribution pattern. The protective layer may comprise aphotosensitive material, which simplifies removal of the protectivematerial from the projecting parts of the redistribution pattern. Theprojecting structure enables the thickness of the protective layer (thepackage layer in a wafer level chip size package) to be reduced, and thesolder joints between the bump electrodes and the redistribution patternto be made more secure, so the semiconductor device is electricallycoupled to external devices with greater reliability.

Fifth Embodiment

The fifth embodiment is a semiconductor device fabricated from a wafer 1as illustrated in FIGS. 33 to 40. The fifth embodiment differs from thefirst embodiment by including interlayer conductive nubs 30, and has adifferent redistribution pattern 10 and bump electrodes 15. Theinterlayer conductive nubs 30, seen in FIGS. 35 to 40, are cylindricalprojections made of the same material as the redistribution pattern 10.The interlayer conductive nubs 30 are formed in the electrode areas 11,making direct electrical contact with the metal underlayer 9, to liftthe redistribution pattern 10 above the protective layer 12.

A fabrication method for the semiconductor device in the fifthembodiment includes the steps PD1 to PD8 illustrated in FIGS. 33 to 40.

Since steps PD1 and PD2 in FIGS. 33 and 34 are the same as steps P1 andP2 in FIGS. 1 and 2 in the first embodiment, descriptions will beomitted.

In step PD3 in FIG. 35, a first photoresist mask 17 is formed. Thisphotoresist mask 17 covers all parts of the metal underlayer 9 exceptfor the electrode areas 11, in which the interlayer conductive nubs 30will be formed. The photoresist mask 17 comprises a positive or negativephotoresist material that is patterned by photolithography. To form theinterlayer conductive nubs 30, the same type of metal as used for theredistribution pattern 10, which will be formed on the interlayerconductive nubs 30 in step PD5, is electro-deposited on the exposedparts of the metal underlayer 9, using the metal underlayer 9 as anegative electrode, to a thickness such that the redistribution pattern10 will project from the front surface of the protective layer 12.

In step PD4 in FIG. 36, the photoresist mask 17 that was formed in stepPD3 is removed with a solvent.

In step PD5 in FIG. 37, a second photoresist mask 17 is formed. Thisphotoresist mask 17 covers all parts of the metal underlayer 9 exceptfor the parts, extending from the surfaces of the electrode pads 5 tothe interlayer conductive nubs 30 in the electrode areas 11, in whichthe redistribution pattern 10 will be formed. The photoresist mask 17comprises a positive or negative photoresist material that is patternedby photolithography. The redistribution pattern 10 is formed on theexposed surface of the metal underlayer 9 as in step P3 in the firstembodiment.

In step PD6 in FIG. 38, the photoresist mask 17 that was formed in stepPD5 is removed with a solvent, and the metal underlayer 9, except forthe part below the redistribution pattern 10 and the interlayerconductive nubs 30, is removed as in step P5 in the first embodiment.

In step PD7 in FIG. 39, a protective layer 12 about 5 m thick is formedas in step PC6 in the fourth embodiment. The parts of the redistributionpattern 10 disposed on the interlayer conductive nubs 30 project fromthe protective layer 12 in the electrode areas 11.

In step PD8 in FIG. 40, hemispherical bump electrodes 15 are formed asin step PC7 in the fourth embodiment. The bump electrodes 15 cover theparts of the redistribution pattern 10 projecting from the front surfaceof the protective layer 12 of the semiconductor wafer 1.

After steps PD1 to PD8 above, the semiconductor wafer 1 is diced intoindividual integrated circuit chips, each including a plurality ofsemiconductor circuit elements. Each chip is a separate WCSPsemiconductor device.

Since a WCSP semiconductor device fabricated as described above includesa plurality of bump electrodes 15 projecting from the front surface ofthe protective layer 12 of the semiconductor device and covering theparts of the redistribution pattern 10 projecting from the protectivelayer 12, instead of being formed on posts, a thin resin layer sufficesto seal the front surface of the semiconductor device. The methoddescribed in the fifth embodiment can therefore be used to fabricateWCSP semiconductor devices with reduced thicknesses.

Use of a photosensitive protective layer 12 to seal the front surface ofthe semiconductor device simplifies the formation of the protectivelayer 12 around the projecting parts of the redistribution pattern 10.Compared with conventional WCSP fabrication processes that form posts,the fabrication process described in the fifth embodiment has fewersteps because it is unnecessary to polish the front surface of the resinprotective layer to expose the ends of the posts before forming the bumpelectrodes. WCSP semiconductor devices according to the fifth embodimentcan accordingly be fabricated more efficiently and in a shorter timethan devices having posts.

The hemispherical bump electrodes 15 cover the parts of theredistribution pattern 10 that are formed on the interlayer conductivenubs 30 and project from the protective layer 12, thereby securingreliable solder joints between the bump electrodes 15 and theredistribution pattern 10. After the semiconductor device is mounted ona printed circuit board or card, the redistribution pattern 10 and theinterlayer conductive nubs 30 absorb external stress applied to the bumpelectrodes 15, making the external electrical connections of thesemiconductor device more reliable.

As described above, in the fifth embodiment, the front surface of asemiconductor device is sealed by a protective layer. Parts of theredistribution pattern project from the protective layer, because theyare formed on nubs on an underlying metal layer, and bump electrodes areplaced on the projecting parts. The protective layer may comprise aphotosensitive material, which simplifies removal of the protectivematerial from the projecting parts of the redistribution pattern. Theprojecting structure enables the thickness of the protective layer (thepackage layer in a wafer level chip size package) to be reduced, and thejoints between the bump electrodes and the redistribution pattern to bemade more secure, so the semiconductor device is electrically coupled toexternal devices with high reliability.

Sixth Embodiment

The sixth embodiment is a semiconductor device identical to thesemiconductor device in the fifth embodiment but fabricated by theprocess illustrated in FIGS. 41 to 48. The photoresist masks 32 seen inFIGS. 43, 44, and 45, which replace the photoresist masks 17 of thefifth embodiment, comprise a positive photoresist material. Thefabrication process will be described below.

Step PE1, illustrated in FIG. 41, and step PE2, illustrated in FIG. 42,are the same as steps P1 and P2 in FIGS. 1 and 2 in the firstembodiment. Descriptions will be omitted.

In step PE3 in FIG. 43, a coat of positive photosensitive resin isspin-coated onto the surface of the metal underlayer 9 and dried. Thedried photosensitive resin is exposed to ultraviolet light through amask that masks all parts except for the electrode areas 11. The exposedphotosensitive resin is then removed by chemical development, exposingthe parts of the metal underlayer 9 on which interlayer conductive nubs30 will be formed, and forming a first photoresist mask 32. The firstphotoresist mask 32 covers all parts of the metal underlayer 9 outsidethe electrode areas 11, and covers the parts in the electrode areas 11in which interlayer conductive nubs 30 will not be formed. Theinterlayer conductive nubs 30 are formed on the exposed parts of themetal underlayer 9 as in step PD3 in the fifth embodiment.

In step PE4 in FIG. 44, the first photoresist mask 32, which was used toform the interlayer conductive nubs 30 in step PE3, is exposed toultraviolet light again through a mask that masks all parts of the wafer1 except for the surfaces of the electrode pads 5, the electrode areas11, and paths leading from the electrode pads 5 to the electrode areas11. The exposed portion of the first photoresist mask 32 is then removedby chemical development, forming a second photoresist mask 32 thatexposes the metal underlayer 9 and the interlayer conductive nubs 30 inthese areas, in which the redistribution pattern 10 will be formed.

In step PE5 in FIG. 45, the redistribution pattern 10 is formed on theexposed surface of the metal underlayer 9 and on the interlayerconductive nubs 30 as in step PD5 in the fifth embodiment.

Steps PE6 to PE8, illustrated in FIGS. 46 to 48, which form theprotective layer 12 and bump electrodes 15, are the same as steps PD6 toPD8 in the fifth embodiment, illustrated in FIGS. 38 to 40, sodescriptions will be omitted.

After steps PE1 to PE8 above, the semiconductor wafer 1 is diced intoindividual integrated circuit chips, each including a plurality ofsemiconductor circuit elements. Each chip is a separate WCSPsemiconductor device.

As described above, in the sixth embodiment, the positive photoresistmask that is used to form the nubs is not removed, but is patterned byexposure to light again in the step that forms the first redistributionpattern. Compared with the fifth embodiment, one photoresist coatingstep is saved. In addition to the effects obtained in the fifthembodiment, WCSP semiconductor devices according to the sixth embodimentcan be fabricated more efficiently and the indirect material cost can bereduced.

Seventh Embodiment

The seventh embodiment is a semiconductor device fabricated from a wafer1 as illustrated in FIGS. 49 to 59. The seventh embodiment differs fromthe fifth and sixth embodiments by including a barrier metal layer 34 ofa metal such as nickel, palladium, or gold. As seen in FIGS. 56 to 59,the barrier metal layer 34 covers all parts of the redistributionpattern 10 except for surfaces of contact between the redistributionpattern 10 and the metal underlayer 9, and between the redistributionpattern 10 and the interlayer conductive nubs 30, to prevent currentfrom leaking from one segment of the redistribution pattern 10 toanother due to moisture taken up by the protective layer 12 and theinterlayer dielectric film 7.

A fabrication method for the semiconductor device in the seventhembodiment includes the steps PF1 to PF11 illustrated in FIGS. 49 to 59.

Steps PF1 to PF5, illustrated in FIGS. 49 to 53, are identical to stepsPD1 to PD5 (FIGS. 33 to 37) in the fifth embodiment, so descriptionswill be omitted.

In step PF6 in FIG. 54, the second photoresist mask 17 that was formedin step PF5 is removed with a solvent.

In step PF7 in FIG. 55, a third photoresist mask 17 is formed. Thisphotoresist mask 17 covers all parts of the metal underlayer 9 exceptfor the part below the redistribution pattern 10 and the interlayerconductive nubs 30 and the parts surrounding the redistribution pattern10, in which the barrier metal layer 34 will be formed. The photoresistmask 17 comprises a positive or negative photoresist material that ispatterned by photolithography.

In step PF8 in FIG. 56, to form the barrier metal layer 34, a barriermetal is electro-deposited on the exposed parts of the metal underlayer9 and the redistribution pattern 10, using the metal underlayer 9 as anegative electrode. The barrier metal layer 34 covers all parts of theredistribution pattern 10 except for the surfaces of contact between theredistribution pattern 10 and the metal underlayer 9, and between theredistribution pattern 10 and the interlayer conductive nubs 30.

In step PF9 in FIG. 57, the photoresist mask 17 that was formed in stepPF7 is removed with a solvent, and the metal underlayer 9, except forthe part below the redistribution pattern 10, the interlayer conductivenubs 30, and the barrier metal layer 34, is removed as in step P5 in thefirst embodiment.

In step PF10 in FIG. 58, a protective layer 12 about 5 μm thick isformed as in step PC6 in the fourth embodiment. The parts of theredistribution pattern 10 and barrier metal layer 34 that are disposedon the interlayer conductive nubs 30 project from the protective layer12 in the electrode areas 11.

In step PF11 in FIG. 59, hemispherical bump electrodes 15 are formed asin step PC7 in the fourth embodiment. The bump electrodes 15 cover theparts of the redistribution pattern 10 that are covered by the barriermetal layer 34 and project from the front surface of the protectivelayer 12 of the semiconductor wafer 1.

After steps PF1 to PF11 above, the semiconductor wafer 1 is diced intoindividual integrated circuit chips, each including a plurality ofsemiconductor circuit elements. Each chip is a separate WCSPsemiconductor device.

Since a WCSP semiconductor device fabricated as described above includesa plurality of bump electrodes 15 projecting from the front surface ofthe protective layer 12 of the semiconductor device, covering projectingparts of the redistribution pattern 10 and barrier metal layer 34instead of being formed on posts, a thin resin layer suffices to sealthe front surface of the semiconductor device. The method described inthe seventh embodiment can therefore be used to fabricate WCSPsemiconductor devices with reduced thicknesses.

Use of a photosensitive protective layer 12 to seal the front surface ofthe semiconductor device simplifies the formation of the protectivelayer 12 around the projecting parts of the redistribution pattern 10and barrier metal layer 34.

The parts of the redistribution pattern 10 and barrier metal layer 34that are covered by the hemispherical bump electrodes 15 are liftedabove the protective layer 12 by the interlayer conductive nubs 30,which enhances the reliability of the solder joints between the bumpelectrodes 15 and the barrier metal layer 34. After the semiconductordevice is mounted on a printed circuit board or card, the redistributionpattern 10 and the interlayer conductive nubs 30 absorb external stressapplied to the bump electrodes 15, making the external electricalconnections of the semiconductor device more reliable.

The barrier metal layer 34 covers all parts of the redistributionpattern 10 except for the surfaces of contact between the redistributionpattern 10 and the metal underlayer 9, and between the redistributionpattern 10 and the interlayer conductive nubs 30, so moisture taken upin the protective layer 12 and the interlayer dielectric film 7 cannotreact with the copper material in the redistribution pattern 10, anddoes not cause current to leak from one segment of the redistributionpattern 10 to another. The semiconductor device accordingly has highmoisture resistance and enhanced reliability.

As described above, in the seventh embodiment, a barrier metal layercovers all parts of the redistribution pattern except for the surfacesof contact between the redistribution pattern and the underlying metallayer, and between the redistribution pattern and the underlying nubs.In addition to the effects obtained in the fifth embodiment, thestructure of the seventh embodiment prevents moisture taken up in theprotective layer and the interlayer dielectric film from reacting withthe redistribution pattern material, and therefore prevents current fromleaking between different parts of the redistribution pattern due tomoisture, so the semiconductor device has high moisture resistance andenhanced reliability.

Eighth Embodiment

The eighth embodiment is a semiconductor device identical to thesemiconductor device in the seventh embodiment, but fabricated by theprocess illustrated in FIGS. 60 to 69, comprising steps PG1 to PG10. Thefabrication process will be described below.

Since steps PG1 to PG5, illustrated in FIGS. 60 to 64, are the same assteps PE1 to PE6 in the sixth embodiment, illustrated in FIGS. 41 to 45.Descriptions will be omitted.

In step PG6 in FIG. 65, a third photoresist mask 32 is formed. After thefirst photoresist mask 32, which defined the interlayer conductive nubs30 in step PG3 (FIG. 62), is exposed to ultraviolet light in step PG4(FIG. 63), forming a second photoresist mask 32, and the redistributionpattern 10 is formed by use of the second photoresist mask 32 in stepPG5 (FIG. 64), in step PG6 (FIG. 65), the second photoresist mask 32 isexposed to ultraviolet light through a mask that masks all parts of thewafer 1 except for the redistribution pattern 10 and a narrow areasurrounding the redistribution pattern 10, these being the parts inwhich the barrier metal layer 34 will be formed. The exposed photoresistmask 32 is then removed by chemical development, uncovering the parts ofthe metal underlayer 9 on which the barrier metal layer 34 will beformed, to form the third photoresist mask 32, which covers the otherparts of the metal underlayer 9.

Steps PG7 to PG10, illustrated in FIGS. 66 to 69, which form theprotective layer 12 and bump electrodes 15, are the same as steps PF8 toPF11 (FIGS. 56 to 59) in the seventh embodiment. Descriptions will beomitted.

After steps PG1 to PG10 above, the semiconductor wafer 1 is diced intoindividual integrated circuit chips, each including a plurality ofsemiconductor circuit elements. Each chip is a separate WCSPsemiconductor device.

As described above, in the eighth embodiment, the positive photoresistmask used to form nubs is left in place after the nubs have been formedand is patterned by two more exposures to light, one defining the firstredistribution pattern, the other defining a barrier metal layer, so itis only necessary to deposit the photoresist material once. In additionto the effects seen in the seventh embodiment, WCSP semiconductordevices according to the eighth embodiment can be fabricated moreefficiently and the indirect material cost can be reduced.

Ninth Embodiment

The ninth embodiment is a semiconductor device fabricated from a wafer 1as illustrated in FIGS. 70 to 77. The ninth embodiment differs from thefirst embodiment by adding a second redistribution pattern 35 toredistribution pattern 10, which will be referred to below as the firstredistribution pattern. The first redistribution pattern 10 also differsfrom the redistribution pattern 10 in the first embodiment in having anedge 10 a disposed within the electrode area 11, as seen in FIGS. 73 to77. As seen in FIGS. 74 to 77, the second redistribution pattern 35covers the surface of the first redistribution pattern 10 and its edge10 a in the electrode areas 11, has an edge 35 a disposed at the edge ofthe electrode area 11, and has an extension 36 extending from that edge35 a onto the surface of the metal underlayer 9.

A fabrication method for the semiconductor device in the ninthembodiment includes the steps PH1 to PH8 illustrated in FIGS. 70 to 77.

Steps PH1, illustrated in FIG. 70, and PH2, illustrated in FIG. 71, arethe same as steps P1 and P2 in FIGS. 1 and 2 in the first embodiment.Descriptions will be omitted.

In step PH3 in FIG. 72, a coat of positive photosensitive resin isapplied to the surface of the metal underlayer 9 by a spin-coatingprocess, and the applied photosensitive resin is dried. The driedphotosensitive resin is exposed to ultraviolet light through a mask thatmasks all parts except for the parts, extending from the surfaces of theelectrode pads 5 to the electrode areas 11, in which the firstredistribution pattern 10 will be formed. The exposed photosensitiveresin is then removed by chemical development, exposing the parts of themetal underlayer 9 on which the first redistribution pattern 10 will beformed, and forming a first photoresist mask 32. The first photoresistmask 32 covers the other parts of the metal underlayer 9. The firstredistribution pattern 10 is formed on the exposed parts of the metalunderlayer 9 as in step P3 in the first embodiment.

In step PH4 in FIG. 73, after the first redistribution pattern 10 hasbeen formed, the photoresist mask 32 is modified to form a secondphotoresist mask 32. Specifically, the first photoresist mask 32 isexposed to ultraviolet light through a mask that masks all parts of thewafer 1 except for the part in which the extensions 36 will be formed,this part extending from the edge 10 a of the first redistributionpattern 10 in each electrode area 11 to a point outside the electrodearea 11. The exposed photoresist mask 32 is then removed by chemicaldevelopment, uncovering the part of the metal underlayer 9 on which theextensions 36 will be formed, and leaving the second photoresist mask32, which covers the other parts of the metal underlayer 9.

In step PH5 in FIG. 74, the second redistribution pattern 35 is formedon the first redistribution pattern 10 and the exposed part of the metalunderlayer 9 by electro-deposition, as in step P3 in the firstembodiment. The part of the second redistribution pattern 35 formed onthe metal underlayer 9 becomes the extensions 36.

In step PH6 in FIG. 75, the remaining part of the photoresist mask 32that was formed in step PH3 is removed with a solvent, and the metalunderlayer 9, except for the part below the first redistribution pattern10 and the extensions 36, is removed as in step P5 in the firstembodiment.

In step PH7 in FIG. 76, a photosensitive resin is applied to the entirefront surface of the semiconductor wafer 1 as in step P6 in the firstembodiment, and the applied photosensitive resin is exposed toultraviolet light with a photoresist mask masking the electrode areas11. The unexposed photosensitive resin is removed by chemicaldevelopment, leaving a protective layer 12 about 5 μm thick withelectrode openings 13 extending to the second redistribution pattern 35in the electrode areas 11, and also exposing the extensions 36.

In step PH8 in FIG. 77, flux is applied to the second redistributionpattern 35, including the edge 35 a and extensions 36, that is exposedat the bottom of each electrode opening 13 in the protective layer 12.Solder balls are emplaced in the electrode openings 13 with a templateas in step P7 in the first embodiment; then a heat treatment process isperformed to melt the solder balls, thereby forming hemispherical bumpelectrodes 15 that project from the front surface of the protectivelayer 12 and are directly joined to the second redistribution pattern 35and the edges 35 a thereof that are exposed at the bottom of theelectrode openings 13.

After steps PH1 to PH8 above, the semiconductor wafer 1 is diced intoindividual integrated circuit chips, each including a plurality ofsemiconductor circuit elements. Each chip is a separate WCSPsemiconductor device.

Since a WCSP semiconductor device fabricated as described above includesa plurality of bump electrodes 15 projecting from the front surface ofthe protective layer 12 of the semiconductor device and directly joinedto the second redistribution pattern 35, instead of being formed onposts, a thin resin layer suffices to seal the front surface of thesemiconductor device. The method described in the ninth embodiment cantherefore be used to fabricate WCSP semiconductor devices with reducedthicknesses.

The use of a photosensitive material for the protective layer 12 thatseals the front surface of the semiconductor device simplifies theformation of the electrode openings 13 for the bump electrodes 15.

The hemispherical bump electrodes 15 cover the second redistributionpattern 35, its edges 35 a, and the extensions 36 that are exposed inthe electrode openings 13 in the protective layer 12. The extensions 36improve the reliability of the solder joints between the bump electrodes15 and the second redistribution pattern 35 by providing a route forescape of air, and by allowing the bump electrodes 15 to make verticalas well as horizontal contact with the second redistribution pattern 35.After the semiconductor device is mounted on a printed circuit board orcard, the second redistribution pattern 35 helps absorb external stressapplied to the bump electrodes 15, making the external electricalconnections of the semiconductor device more reliable.

The second redistribution pattern 35 is deposited on the firstredistribution pattern 10, so the combined thickness of the secondredistribution pattern 35 and the first redistribution pattern 10 in theninth embodiment is twice the thickness of the redistribution pattern inthe first embodiment, thereby providing a WCSP semiconductor deviceswith improved electrical properties and higher added value.

The positive photoresist mask used to form the first redistributionpattern 10 is left in place after the first redistribution pattern 10 isformed and is patterned by one more exposure to light, defining thesecond redistribution pattern 35, so it is only necessary to deposit thephotoresist material once. WCSP semiconductor devices according to theninth embodiment can accordingly be fabricated efficiently and theindirect material cost can be reduced.

As described above, in the ninth embodiment, a second redistributionpattern is deposited on the first redistribution pattern. The frontsurface of the semiconductor device is sealed by a protective layerhaving openings exposing parts of the second redistribution pattern,including extension parts. The openings are covered by bump electrodesthat are electrically coupled to the parts of the second redistributionpattern disposed within the openings. This structure enables thethickness of the protective layer (the package layer in a wafer levelchip size package) to be reduced because the electrodes are connecteddirectly to the top surfaces and edges of the second redistributionpattern. The protective layer may comprise a photosensitive material,which simplifies the formation of the openings for the electrodes. Thecombined thickness of the first and second redistribution patterns inthe ninth embodiment is twice the thickness of the redistributionpattern in the first embodiment, thereby providing WCSP semiconductordevices with improved electrical properties and higher added value.

The invention is not limited to the embodiments described above; thoseskilled in the art will recognize that further variations are possiblewithin the scope of the invention, which is defined in the appendedclaims.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate having a circuit element formed on a surface ofthe semiconductor substrate; an electrode pad formed on the surface ofthe semiconductor substrate, and electrically coupled to the circuitelement; a first dielectric film formed over the surface of thesemiconductor substrate, and having a through hole that extends to theelectrode pad; a conductive pattern, electrically coupled to theelectrode pad, extending from the through hole to an upper surface ofthe first dielectric film; a second dielectric film covering both thefirst dielectric film and the conductive pattern; a conductive nub,electrically coupled to the conductive pattern, extending upwardly fromthe conductive pattern in the second dielectric film and projectingupwardly from an upper surface of the second dielectric film in avertical direction perpendicular to the surface of the semiconductorsubstrate, the conductive nub being formed in an area other than theupper surface of the second dielectric film; and a bump electrode formedon the conductive nub, covering at least part of the upwardly projectedportion of the conductive nub.
 2. The semiconductor device of claim 1,wherein the conductive nub is formed in the area other than an upperarea that is in the vertical direction above the upper surface of thesecond dielectric film.
 3. The semiconductor device of claim 1, whereinthe conductive nub is formed in the area other than an area directlyabove the electrode pad.
 4. The semiconductor device of claim 1, furthercomprising a metal underlayer disposed between the conductive patternand the first dielectric film.
 5. The semiconductor device of claim 1,further comprising a third dielectric film disposed between the firstdielectric film and the surface of the semiconductor substrate.
 6. Thesemiconductor device of claim 1, wherein the second dielectric film ismade from a photosensitive resin.